[ltt-dev] [URCU PATCH] cmm: provide lightweight rmb/wmb on PPC

[Paolo Bonzini]

lwsync orders loads with respect to other loads, and stores with respect
to other stores.  eieio instead only orders stores.  Use them to
implement rmb/wmb/smp_wmb.
---
 urcu/arch/ppc.h |    9 ++++++++-
 1 files changed, 8 insertions(+), 1 deletions(-)

diff --git a/urcu/arch/ppc.h b/urcu/arch/ppc.h
index a03d688..3a6c702 100644
--- a/urcu/arch/ppc.h
+++ b/urcu/arch/ppc.h
@@ -32,7 +32,14 @@ extern "C" {
 /* Include size of POWER5+ L3 cache lines: 256 bytes */
 #define CAA_CACHE_LINE_SIZE	256
 
-#define cmm_mb()    asm volatile("sync":::"memory")
+#define cmm_mb()	 asm volatile("sync":::"memory")
+#define cmm_rmb()	 asm volatile("lwsync":::"memory")
+#define cmm_wmb()	 asm volatile("lwsync":::"memory")
+
+/* eieio is good for a write memory barrier, assuming we don't
+ * need to order cacheable and non-cacheable stores with respect
+ * to each other.  */
+#define cmm_smp_wmb()    asm volatile("eieio":::"memory")
 
 #define mftbl()						\
 	({ 						\
-- 
1.7.6