[ltt-dev] [URCU PATCH] cmm: provide lightweight rmb/wmb on PPC

[Mathieu Desnoyers]

* Paolo Bonzini (pbonzini at redhat.com) wrote:
> lwsync orders loads with respect to other loads, and stores with respect
> to other stores.  eieio instead only orders stores.  Use them to
> implement rmb/wmb/smp_wmb.
> ---
>  urcu/arch/ppc.h |    9 ++++++++-
>  1 files changed, 8 insertions(+), 1 deletions(-)
> 
> diff --git a/urcu/arch/ppc.h b/urcu/arch/ppc.h
> index a03d688..3a6c702 100644
> --- a/urcu/arch/ppc.h
> +++ b/urcu/arch/ppc.h
> @@ -32,7 +32,14 @@ extern "C" {
>  /* Include size of POWER5+ L3 cache lines: 256 bytes */
>  #define CAA_CACHE_LINE_SIZE	256
>  
> -#define cmm_mb()    asm volatile("sync":::"memory")
> +#define cmm_mb()	 asm volatile("sync":::"memory")
> +#define cmm_rmb()	 asm volatile("lwsync":::"memory")
> +#define cmm_wmb()	 asm volatile("lwsync":::"memory")

I don't think lwsync orders non-cacheable memory operations. Therefore,
is it the right choice for cmm_rmb/cmm_wmb ?

It might be a good choice for cmm_smp_rmb/cmm_smp_wmb though.

> +
> +/* eieio is good for a write memory barrier, assuming we don't
> + * need to order cacheable and non-cacheable stores with respect
> + * to each other.  */
> +#define cmm_smp_wmb()    asm volatile("eieio":::"memory")

For this one, I wonder which of lwsync or eieio perform best ? But the
question that arises is whether lwsync is available on all PowerPC
flavors, and if not, which. We may want to have a configure/compile
option to specialize the output generated depending on the powerpc
flavor.

If eieio is slower than lwsync on recent powerpc, then slowing down new
generations for speedup of older generations seems like a global loss.

Thanks,

Mathieu

>  
>  #define mftbl()						\
>  	({ 						\
> -- 
> 1.7.6
> 
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-- 
Mathieu Desnoyers
Operating System Efficiency R&D Consultant
EfficiOS Inc.
http://www.efficios.com