[ltt-dev] SMP issues on ARM

[Mathieu Desnoyers]

* Gaurav Singh (gausinghnsit at gmail.com) wrote:
> Hi,
> I am working on an ARM cortex based SMP system and am interested in
> calculating spinlock hold times. I am also looking to add
> instrumentation for cache related code. (finding no. of cache hits and
> misses etc.)
> 
> For spinlock hold time I propose using tracemarks in
> kernel/spinlocks.c for lock and unlock. The difficult part is finding
> the name of the spinlock in use. We can probably use a structure to
> store names of spinlocks and keep adding names as and when new locks
> are encountered. Sounds a bit simplistic [:-)] - any better ideas? New
> LTTV plugins will need to be developed to view spinlock information.
> 

Hello,

The instrumentation is already there : we have tracepoints in
kernel/lockdep.c.

> For cache related issues - has there been any work on this topic? Any
> pointers are welcome.
> 

Nope, but ideally we would need to sample performance counters from the
tracing code when some tracepoints are hit, and/or periodically from a
timer, and/or to have an interrupt every X number of performance counter
events. Integration with oprofile and/or perfmon2 would probably the
best thing to do.

The basic idea would be to configure the performance monitoring counters
as "system-side counters" (_not_ per process/per-thread counter).

Mathieu


> Thanks and Regards
> Gaurav
> 

-- 
Mathieu Desnoyers
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