<html><body><div style="font-family: arial, helvetica, sans-serif; font-size: 12pt; color: #000000"><div><span id="zwchr" data-marker="__DIVIDER__">----- On Jul 21, 2016, at 4:47 PM, Mark E. Dawson <medawsonjr@yahoo.com> wrote:<br></span></div><div data-marker="__QUOTED_TEXT__"><blockquote style="border-left:2px solid #1010FF;margin-left:5px;padding-left:5px;color:#000;font-weight:normal;font-style:normal;text-decoration:none;font-family:Helvetica,Arial,sans-serif;font-size:12pt;"><div style="color:#000; background-color:#fff; font-family:HelveticaNeue, Helvetica Neue, Helvetica, Arial, Lucida Grande, sans-serif;font-size:16px"><div id="yui_3_16_0_ym19_1_1469131414329_10925">All,</div><div id="yui_3_16_0_ym19_1_1469131414329_10925"><br></div><div id="yui_3_16_0_ym19_1_1469131414329_10925">I've read the documentation regarding reader throughput drop-offs with high update rates due to the pointer exchanging between readers-writers, and the general admonition of using URCU only for mostly-read workloads with relatively infrequent updates.</div><div id="yui_3_16_0_ym19_1_1469131414329_10925"><br></div><div id="yui_3_16_0_ym19_1_1469131414329_10925">However, is there a general rule-of-thumb suggestion for highest recommended update rate sustainable for optimal performance with URCU (in particular, the QSBR flavor) for highly threaded applications deployed on high core count machines (Intel)? The example case would be a single updater and 20 - 30 reader threads.</div></div></blockquote><div><br></div><div>Hi Mark,<br data-mce-bogus="1"></div><div><br data-mce-bogus="1"></div><div>We have some relevant measurements in the supplementary material of:<br data-mce-bogus="1"></div><div><br data-mce-bogus="1"></div><div>Desnoyers, Mathieu, McKenney, Paul. E., Stern, Alan S., Dagenais, Michel R. and Walpole, Jonathan, <em>User-Level Implementations of Read-Copy Update</em>. <a href="http://www.computer.org/portal/web/tpds/" data-mce-href="http://www.computer.org/portal/web/tpds/">IEEE Transaction on Parallel and Distributed Systems</a>, 23 (2): 375-382 (2012).</div><div><br data-mce-bogus="1"></div><div>A copy can be found at http://www.efficios.com/publications<br data-mce-bogus="1"></div><div><br data-mce-bogus="1"></div><div>See p. 10 of supplementary material, Fig. 14:<br data-mce-bogus="1"></div><div><br data-mce-bogus="1"></div><div>"Comparison of Pointer Exchange and Ideal RCU Update Overhead, 8-core Intel Xeon, Logarithmic Scale"<br data-mce-bogus="1"></div><div><br data-mce-bogus="1"></div>Since you are doing pointer exchange, you will want to look at the "QSBR"</div><div data-marker="__QUOTED_TEXT__">line, which stays at 1000M reads/s up to 100000 updates/s, and then starts</div><div data-marker="__QUOTED_TEXT__">dropping.</div><div data-marker="__QUOTED_TEXT__"><br data-mce-bogus="1"></div><div data-marker="__QUOTED_TEXT__">On the 64-core POWER5+ (Fig. 15), read speed starts dropping near 100000</div><div data-marker="__QUOTED_TEXT__">updates/s too.<br data-mce-bogus="1"></div><div data-marker="__QUOTED_TEXT__"><br data-mce-bogus="1"></div><div data-marker="__QUOTED_TEXT__">Thanks,</div><div data-marker="__QUOTED_TEXT__"><br data-mce-bogus="1"></div><div data-marker="__QUOTED_TEXT__">Mathieu<br><blockquote style="border-left:2px solid #1010FF;margin-left:5px;padding-left:5px;color:#000;font-weight:normal;font-style:normal;text-decoration:none;font-family:Helvetica,Arial,sans-serif;font-size:12pt;">_______________________________________________<br>lttng-dev mailing list<br>lttng-dev@lists.lttng.org<br>https://lists.lttng.org/cgi-bin/mailman/listinfo/lttng-dev<br></blockquote></div><div><br></div><div data-marker="__SIG_POST__">-- <br></div><div>Mathieu Desnoyers<br>EfficiOS Inc.<br>http://www.efficios.com</div></div></body></html>