[ltt-dev] [URCU PATCH] add simple mips support
Mathieu Desnoyers
mathieu.desnoyers at efficios.com
Wed Sep 7 11:40:46 EDT 2011
* Mathieu Desnoyers (mathieu.desnoyers at efficios.com) wrote:
> * Jason Wessel (jason.wessel at windriver.com) wrote:
> > Add a simple URCU implementation for MIPS for the explicit purpose of
> > using it with UST.
> >
> > The simple implementation was borrowed from the ARM specific
> > architecture implementation that already existed in URCU.
> >
> > Signed-off-by: Jason Wessel <jason.wessel at windriver.com>
> > ---
> > README | 13 ++++++-----
> > configure.ac | 1 +
> > urcu/arch_mips.h | 54 ++++++++++++++++++++++++++++++++++++++++++++++
> > urcu/uatomic_arch_mips.h | 50 ++++++++++++++++++++++++++++++++++++++++++
> > 4 files changed, 112 insertions(+), 6 deletions(-)
> > create mode 100644 urcu/arch_mips.h
> > create mode 100644 urcu/uatomic_arch_mips.h
> >
> > diff --git a/README b/README
> > index f7f0dec..fdfdcd5 100644
> > --- a/README
> > +++ b/README
> > @@ -24,11 +24,12 @@ BUILDING
> > ARCHITECTURES SUPPORTED
> > -----------------------
> >
> > -Currently, x86 (i386, i486, i586, i686), x86 64-bit, PowerPC 32/64, S390, S390x,
> > -ARM, Alpha, ia64 and Sparcv9 32/64 are supported. Only tested on Linux so
> > -far, but should theoretically work on other operating systems.
> > +Currently, x86 (i386, i486, i586, i686), x86 64-bit, MIPS, PowerPC
> > +32/64, S390, S390x, ARM, Alpha, ia64 and Sparcv9 32/64 are
> > +supported. Only tested on Linux so far, but should theoretically work
> > +on other operating systems.
> >
> > -ARM depends on running a Linux kernel 2.6.15 or better.
> > +ARM and MIPS depend on running a Linux kernel 2.6.15 or better.
> >
> > The gcc compiler versions 3.3, 3.4, 4.0, 4.1, 4.2, 4.3, 4.4 and 4.5 are
> > supported, with the following exceptions:
> > @@ -38,8 +39,8 @@ supported, with the following exceptions:
> > therefore not compatible with liburcu on x86 32-bit (i386, i486, i586, i686).
> > The problem has been reported to the gcc community:
> > http://www.mail-archive.com/gcc-bugs@gcc.gnu.org/msg281255.html
> > -- Alpha, ia64 and ARM architectures depend on 4.x gcc with atomic builtins
> > - support.
> > +- Alpha, ia64, MIPS and ARM architectures depend on 4.x gcc with
> > + atomic builtins support.
> >
> >
> > QUICK START GUIDE
> > diff --git a/configure.ac b/configure.ac
> > index 3c61abc..1a51c68 100644
> > --- a/configure.ac
> > +++ b/configure.ac
> > @@ -54,6 +54,7 @@ case $host_cpu in
> > alpha*) ARCHTYPE="alpha" ;;
> > ia64) ARCHTYPE="gcc" ;;
> > arm*) ARCHTYPE="arm" ;;
> > + mips*) ARCHTYPE="mips" ;;
> > *) ARCHTYPE="unknown";;
> > esac
> >
> > diff --git a/urcu/arch_mips.h b/urcu/arch_mips.h
> > new file mode 100644
> > index 0000000..25e033c
> > --- /dev/null
> > +++ b/urcu/arch_mips.h
> > @@ -0,0 +1,54 @@
> > +#ifndef _URCU_ARCH_MIPS_H
> > +#define _URCU_ARCH_MIPS_H
> > +
> > +/*
> > + * arch_mips.h: trivial definitions for the MIPS architecture.
> > + *
> > + * Copyright (c) 2010 Paul E. McKenney, IBM Corporation.
> > + * Copyright (c) 2009 Mathieu Desnoyers <mathieu.desnoyers at efficios.com>
> > + *
> > + * This library is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU Lesser General Public
> > + * License as published by the Free Software Foundation; either
> > + * version 2.1 of the License, or (at your option) any later version.
> > + *
> > + * This library is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> > + * Lesser General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU Lesser General Public
> > + * License along with this library; if not, write to the Free Software
> > + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
> > + */
> > +
> > +#include <urcu/compiler.h>
> > +#include <urcu/config.h>
> > +
> > +#ifdef __cplusplus
> > +extern "C" {
> > +#endif
>
> The ARM version has:
>
> #ifdef CONFIG_ARM_HAVE_DMB
> #define cmm_mb() asm volatile("dmb":::"memory")
> #define cmm_rmb() asm volatile("dmb":::"memory")
> #define cmm_wmb() asm volatile("dmb":::"memory")
> #endif /* CONFIG_ARM_HAVE_DMB */
>
> Looking at how the Linux kernel works, we should have:
>
> For CAVIUM_OCTEON:
>
> smp_mb(), smp_rmb() and smp_wmb() mapped to, respectively:
>
> __sync(), barrier() and __syncw().
>
> (see barrier.h for their definition)
>
> For others (SMP):
>
> smp_mb(), smp_rmb() and smp_wmb() all mapped to:
>
> __asm__ __volatile__("sync" : : : "memory")
>
> for UP:
>
> smp_mb(), smp_rmb() and smp_wmb() all mapped to:
>
> barrier()
>
> If we look at arch_generic.h, it is supposed to map
>
> #define cmm_mb() __sync_synchronize()
>
> so it _should_ use the compiler builtin memory barrier, but it seems to
> fail on your architecture. Looking at the assembly output of this
> builtin might give us interesting information about why it fails.
>
Hi Jason,
Any plan on re-submitting a urcu patch for MIPS ? I think the kernel bug
you hit with the urcu stress-tests got fixed ? (can we have the fix
commit id ?) And some basic configure --with-mips-octeon would probably
be good enough for Cavium Octeon support.
Thanks,
Mathieu
> Thanks,
>
> Mathieu
>
>
> > +
> > +#include <stdlib.h>
> > +#include <sys/time.h>
> > +
> > +typedef unsigned long long cycles_t;
> > +
> > +static inline cycles_t caa_get_cycles (void)
> > +{
> > + cycles_t thetime;
> > + struct timeval tv;
> > +
> > + if (gettimeofday(&tv, NULL) != 0)
> > + return 0;
> > + thetime = ((cycles_t)tv.tv_sec) * 1000000ULL + ((cycles_t)tv.tv_usec);
> > + return (cycles_t)thetime;
> > +}
> > +
> > +#ifdef __cplusplus
> > +}
> > +#endif
> > +
> > +#include <urcu/arch_generic.h>
> > +
> > +#endif /* _URCU_ARCH_MIPS_H */
> > diff --git a/urcu/uatomic_arch_mips.h b/urcu/uatomic_arch_mips.h
> > new file mode 100644
> > index 0000000..a071fcb
> > --- /dev/null
> > +++ b/urcu/uatomic_arch_mips.h
> > @@ -0,0 +1,50 @@
> > +#ifndef _URCU_ARCH_UATOMIC_MIPS_H
> > +#define _URCU_ARCH_UATOMIC_MIPS_H
> > +
> > +/*
> > + * Atomics for MIPS. This approach is usable on kernels back to 2.6.15.
> > + *
> > + * Copyright (c) 1991-1994 by Xerox Corporation. All rights reserved.
> > + * Copyright (c) 1996-1999 by Silicon Graphics. All rights reserved.
> > + * Copyright (c) 1999-2004 Hewlett-Packard Development Company, L.P.
> > + * Copyright (c) 2009 Mathieu Desnoyers
> > + * Copyright (c) 2010 Paul E. McKenney, IBM Corporation
> > + * (Adapted from uatomic_arch_ppc.h)
> > + *
> > + * THIS MATERIAL IS PROVIDED AS IS, WITH ABSOLUTELY NO WARRANTY EXPRESSED
> > + * OR IMPLIED. ANY USE IS AT YOUR OWN RISK.
> > + *
> > + * Permission is hereby granted to use or copy this program
> > + * for any purpose, provided the above notices are retained on all copies.
> > + * Permission to modify the code and to distribute modified code is granted,
> > + * provided the above notices are retained, and a notice that the code was
> > + * modified is included with the above copyright notice.
> > + *
> > + * Code inspired from libuatomic_ops-1.2, inherited in part from the
> > + * Boehm-Demers-Weiser conservative garbage collector.
> > + */
> > +
> > +#include <urcu/compiler.h>
> > +#include <urcu/system.h>
> > +
> > +#ifdef __cplusplus
> > +extern "C" {
> > +#endif
> > +
> > +/* xchg */
> > +#define uatomic_xchg(addr, v) __sync_lock_test_and_set(addr, v)
> > +
> > +/* cmpxchg */
> > +#define uatomic_cmpxchg(addr, old, _new) \
> > + __sync_val_compare_and_swap(addr, old, _new)
> > +
> > +/* uatomic_add_return */
> > +#define uatomic_add_return(addr, v) __sync_add_and_fetch(addr, v)
> > +
> > +#ifdef __cplusplus
> > +}
> > +#endif
> > +
> > +#include <urcu/uatomic_generic.h>
> > +
> > +#endif /* _URCU_ARCH_UATOMIC_MIPS_H */
> > --
> > 1.7.1
> >
>
> --
> Mathieu Desnoyers
> Operating System Efficiency R&D Consultant
> EfficiOS Inc.
> http://www.efficios.com
>
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>
--
Mathieu Desnoyers
Operating System Efficiency R&D Consultant
EfficiOS Inc.
http://www.efficios.com
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