[ltt-dev] Userspace RCU: ARMv7 memory barriers

[Mathieu Desnoyers]

Hi Paul, Hi Jason,

In Userspace RCU commit f63b71415e6a4c19a6c80d2f0464a0cface53af8

I did:

    ARM: use dmb for rmb and wmb in addition to mb

-#define cmm_mb()    asm volatile("dmb":::"memory")
+#define cmm_mb()       asm volatile("dmb":::"memory")
+#define cmm_rmb()      asm volatile("dmb":::"memory")
+#define cmm_wmb()      asm volatile("dmb":::"memory")

But forgot to ping Paul about this. Maybe there was a reason for not
using dmb for rmb and wmb in the first place ? If it is the case, I
think it would be worth a comment in the code.

We should note that Linux maps mb, rmb and wmb to "dmb". For v6, mb maps
to dsb(); outer_sync(); if DMA memory is bufferable. I wonder if our
"mb" should provide order wrt DMA accesses ? We should probably document
that. I guess that providing this guarantee from userspace might turn
out to be harder than from the kernel.

I also notice that we should probably exclude the Intel XSC3 ARMv6 from
our list of supported ARM architectures, because it seems to require
access ordering even if it is a UP architecture (but it's possibly only
for DMA ?).

Thanks,

Mathieu

-- 
Mathieu Desnoyers
Operating System Efficiency R&D Consultant
EfficiOS Inc.
http://www.efficios.com