[ltt-dev] lttv unable to execute textDump on MIPS multicore target
Naresh Bhat
nareshgbhat at gmail.com
Wed Feb 16 06:26:34 EST 2011
Hi Mathieu/David,
Thank you very much for all your support.
Here is my back ported working patch for 2.6.32 with lttng patch set 0.188
kernel
====================================================================================================
Description:
fix lttng mips use 64 bit counter for trace clock
and fix octeon get_cycles
Signed-off-by: David Daney <ddaney at caviumnetworks.com>
Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers at efficios.com>
Signed-off-by: Naresh Bhat <nareshgbhat at gmail.com>
---
arch/mips/Kconfig | 7 ++++
arch/mips/include/asm/octeon/trace-clock.h | 43
++++++++++++++++++++++++++++
arch/mips/include/asm/timex.h | 35 ++++++++++++++++++++++-
arch/mips/include/asm/trace-clock.h | 6 ++++
arch/mips/kernel/smp.c | 2 +
5 files changed, 92 insertions(+), 1 deletions(-)
create mode 100644 arch/mips/include/asm/octeon/trace-clock.h
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 2aaf0a3..8e19a6d 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -1739,10 +1739,17 @@ config CPU_R4400_WORKAROUNDS
config HAVE_GET_CYCLES_32
def_bool y
depends on !CPU_R4400_WORKAROUNDS
+ depends on !CPU_CAVIUM_OCTEON
select HAVE_TRACE_CLOCK
select HAVE_TRACE_CLOCK_32_TO_64
select HAVE_UNSYNCHRONIZED_TSC
+config HAVE_GET_CYCLES
+ def_bool y
+ depends on CPU_CAVIUM_OCTEON
+ select HAVE_TRACE_CLOCK
+ select HAVE_UNSYNCHRONIZED_TSC
+
#
# Use the generic interrupt handling code in kernel/irq/:
#
diff --git a/arch/mips/include/asm/octeon/trace-clock.h
b/arch/mips/include/asm/octeon/trace-clock.h
new file mode 100644
index 0000000..dd408a0
--- /dev/null
+++ b/arch/mips/include/asm/octeon/trace-clock.h
@@ -0,0 +1,43 @@
+/*
+** Copyright (C) 2005,2008 Mathieu Desnoyers
+**
+** Trace clock MIPS Octeon definitions.
+**/
+
+#ifndef _ASM_MIPS_OCTEON_TRACE_CLOCK_H
+#define _ASM_MIPS_OCTEON_TRACE_CLOCK_H
+
+#include <asm/octeon/octeon.h>
+
+#define TC_HW_BITS 64
+
+static inline u32 trace_clock_read32(void)
+{
+ return (u32)read_c0_cvmcount(); /* only need the 32 LSB */
+}
+
+static inline u64 trace_clock_read64(void)
+{
+ return read_c0_cvmcount();
+}
+
+static inline u64 trace_clock_frequency(void)
+{
+ return octeon_get_clock_rate();
+}
+
+static inline u32 trace_clock_freq_scale(void)
+{
+ return 1;
+}
+
+static inline void get_trace_clock(void)
+{
+ return;
+}
+
+static inline void put_trace_clock(void)
+{
+ return;
+}
+#endif /* _ASM_MIPS_OCTEON_TRACE_CLOCK_H */
diff --git a/arch/mips/include/asm/timex.h b/arch/mips/include/asm/timex.h
index 10c8dd8..2d0c8ae 100644
--- a/arch/mips/include/asm/timex.h
+++ b/arch/mips/include/asm/timex.h
@@ -42,9 +42,42 @@ extern unsigned int mips_hpt_frequency;
* will result in the timer interrupt getting lost.
*/
+#if defined(CONFIG_CPU_CAVIUM_OCTEON)
+/* Since the Octeon supports a 64 bit cycle counter we might as well use
+ * it. We can't use it with an O32 kernel since 64bit registers are not
+ * saved. */
+typedef unsigned long cycles_t;
+#else
typedef unsigned int cycles_t;
+#endif
+
+#ifdef CONFIG_HAVE_GET_CYCLES
+# ifdef CONFIG_CPU_CAVIUM_OCTEON
+static inline cycles_t get_cycles(void)
+{
+ return read_c0_cvmcount();
+}
+
+static inline void get_cycles_barrier(void)
+{
+}
+
+static inline cycles_t get_cycles_rate(void)
+{
+ return mips_hpt_frequency;
+}
+
+extern int test_tsc_synchronization(void);
+extern int _tsc_is_sync;
+static inline int tsc_is_sync(void)
+{
+ return _tsc_is_sync;
+}
+# else /* #ifdef CONFIG_CPU_CAVIUM_OCTEON */
+# error "64-bit get_cycles() supported only on Cavium Octeon MIPS
architectures"
+# endif /* #else #ifdef CONFIG_CPU_CAVIUM_OCTEON */
+#elif defined(CONFIG_HAVE_GET_CYCLES_32)
-#ifdef CONFIG_HAVE_GET_CYCLES_32
static inline cycles_t get_cycles(void)
{
return read_c0_count();
diff --git a/arch/mips/include/asm/trace-clock.h
b/arch/mips/include/asm/trace-clock.h
index 3d8cb0f..0c7a407 100644
--- a/arch/mips/include/asm/trace-clock.h
+++ b/arch/mips/include/asm/trace-clock.h
@@ -12,6 +12,11 @@
#define TRACE_CLOCK_MIN_PROBE_DURATION 200
+#ifdef CONFIG_CPU_CAVIUM_OCTEON
+# include <asm/octeon/trace-clock.h>
+#else /* !CONFIG_CPU_CAVIUM_OCTEON */
+
+
/*
* Number of hardware clock bits. The higher order bits are expected to be
0.
* If the hardware clock source has more than 32 bits, the bits higher than
the
@@ -65,6 +70,7 @@ static inline void put_trace_clock(void)
{
put_synthetic_tsc();
}
+#endif /* CONFIG_CPU_CAVIUM_OCTEON */
static inline void set_trace_clock_is_sync(int state)
{
diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c
index f8c50d1..42083eb 100644
--- a/arch/mips/kernel/smp.c
+++ b/arch/mips/kernel/smp.c
@@ -159,7 +159,9 @@ void __init smp_cpus_done(unsigned int max_cpus)
{
mp_ops->cpus_done();
synchronise_count_master();
+#ifdef CONFIG_HAVE_UNSYNCHRONIZED_TSC
test_tsc_synchronization();
+#endif
}
/* called from main before smp_init() */
--
1.6.3.3.329.g39ec5
====================================================================================================
On Tue, Feb 15, 2011 at 7:39 PM, Mathieu Desnoyers <
compudj at krystal.dyndns.org> wrote:
> * Naresh Bhat (nareshgbhat at gmail.com) wrote:
> > Hi Mathieu/David,
> >
> > The compilation issue is solved and I am able to run the lttng on 2.6.32
> > kernel with 0.188 patch set on Octeon board. I have fully applied your
> last
> > patch and partially applied the earlier patch.
> > *
> > Thanks and Regards
>
> Great! I'm glad it works for you. I'll prepare a LTTng release with
> these fixes shortly.
>
> Mathieu
>
> > -Naresh Bhat*
> >
> > On Tue, Feb 15, 2011 at 7:00 PM, Naresh Bhat <nareshgbhat at gmail.com>
> wrote:
> >
> > > Hi Mathieu/David,
> > >
> > > Thank you very much. The patch is applied without any issues. But
> facing
> > > the linking errors. Is there any configuration missing in Kconfig ?
> > >
> > > *
> > > Thanks and Regards
> > > -Naresh Bhat*
> > > *
> > > Linking error log:*
> > >
> > >
> > >
> ========================================================================================================
> > > ..................
> > > ......................
> > > ..............................
> > > AR arch/mips/lib/lib.a
> > > LD vmlinux.o
> > > MODPOST vmlinux.o
> > > GEN .version
> > > CHK include/linux/compile.h
> > > UPD include/linux/compile.h
> > > CC init/version.o
> > > LD init/built-in.o
> > > LD .tmp_vmlinux1
> > > ltt/built-in.o: In function `ltt_trace_destroy':
> > > (.text.ltt_trace_destroy+0x6c): undefined reference to
> `put_synthetic_tsc'
> > > ltt/built-in.o: In function `ltt_trace_alloc':
> > > (.text.ltt_trace_alloc+0x5c): undefined reference to
> `get_synthetic_tsc'
> > > ltt/built-in.o: In function `ltt_trace_alloc':
> > > (.text.ltt_trace_alloc+0x164): undefined reference to
> > > `trace_clock_read_synthetic_tsc'
> > > ltt/built-in.o: In function `ltt_trace_alloc':
> > > (.text.ltt_trace_alloc+0x454): undefined reference to
> `put_synthetic_tsc'
> > > ltt/built-in.o: In function `ltt_trace_alloc':
> > > (.text.ltt_trace_alloc+0x4b4): undefined reference to
> `put_synthetic_tsc'
> > > ltt/built-in.o: In function `ltt_trace_alloc':
> > > (.text.ltt_trace_alloc+0x4f8): undefined reference to
> `put_synthetic_tsc'
> > > ltt/built-in.o: In function `ltt_reserve_slot_lockless_slow':
> > > (.text.ltt_reserve_slot_lockless_slow+0xa8): undefined reference to
> > > `trace_clock_read_synthetic_tsc'
> > > ltt/built-in.o: In function `ltt_force_switch_lockless_slow':
> > > (.text.ltt_force_switch_lockless_slow+0x44): undefined reference to
> > > `trace_clock_read_synthetic_tsc'
> > > ltt/built-in.o: In function `_ltt_specialized_trace':
> > > (.text._ltt_specialized_trace+0x1cc): undefined reference to
> > > `trace_clock_read_synthetic_tsc'
> > > make: *** [.tmp_vmlinux1] Error 1
> > > #
> > >
> > >
> ==============================================================================================
> > > ===
> > >
> > >
> > >
> > > On Tue, Feb 15, 2011 at 9:02 AM, Mathieu Desnoyers <
> > > compudj at krystal.dyndns.org> wrote:
> > >
> > >> Is the following patch less confusing ?
> > >>
> > >>
> > >> MIPS: octeon fix get_cycles
> > >>
> > >> Make sure get_cycles(), used by kernel/time/tsc-sync.c TSC
> synchronicity
> > >> checker, works fine on octeon by using the full 64-bits.
> > >>
> > >> Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers at efficios.com>
> > >> ---
> > >> arch/mips/Kconfig | 11 +++++++++--
> > >> arch/mips/include/asm/timex.h | 31 ++++++++++++++++++++++++++++++-
> > >> 2 files changed, 39 insertions(+), 3 deletions(-)
> > >>
> > >> Index: linux-2.6-lttng/arch/mips/Kconfig
> > >> ===================================================================
> > >> --- linux-2.6-lttng.orig/arch/mips/Kconfig
> > >> +++ linux-2.6-lttng/arch/mips/Kconfig
> > >> @@ -1949,9 +1949,16 @@ config CPU_R4400_WORKAROUNDS
> > >> config HAVE_GET_CYCLES_32
> > >> def_bool y
> > >> depends on !CPU_R4400_WORKAROUNDS
> > >> + depends on !CPU_CAVIUM_OCTEON
> > >> select HAVE_TRACE_CLOCK
> > >> - select HAVE_TRACE_CLOCK_32_TO_64 if (!CPU_CAVIUM_OCTEON)
> > >> - select HAVE_UNSYNCHRONIZED_TSC if (!CPU_CAVIUM_OCTEON)
> > >> + select HAVE_TRACE_CLOCK_32_TO_64
> > >> + select HAVE_UNSYNCHRONIZED_TSC
> > >> +
> > >> +config HAVE_GET_CYCLES
> > >> + def_bool y
> > >> + depends on CPU_CAVIUM_OCTEON
> > >> + select HAVE_TRACE_CLOCK
> > >> + select HAVE_UNSYNCHRONIZED_TSC
> > >>
> > >> #
> > >> # - Highmem only makes sense for the 32-bit kernel.
> > >> Index: linux-2.6-lttng/arch/mips/include/asm/timex.h
> > >> ===================================================================
> > >> --- linux-2.6-lttng.orig/arch/mips/include/asm/timex.h
> > >> +++ linux-2.6-lttng/arch/mips/include/asm/timex.h
> > >> @@ -42,9 +42,36 @@ extern unsigned int mips_hpt_frequency;
> > >> * will result in the timer interrupt getting lost.
> > >> */
> > >>
> > >> +#ifdef CONFIG_HAVE_GET_CYCLES
> > >> +# ifdef CONFIG_CPU_CAVIUM_OCTEON
> > >> +typedef unsigned int cycles_t;
> > >> +
> > >> +static inline cycles_t get_cycles(void)
> > >> +{
> > >> + return read_c0_cvmcount();
> > >> +}
> > >> +
> > >> +static inline void get_cycles_barrier(void)
> > >> +{
> > >> +}
> > >> +
> > >> +static inline cycles_t get_cycles_rate(void)
> > >> +{
> > >> + return mips_hpt_frequency;
> > >> +}
> > >> +
> > >> +extern int test_tsc_synchronization(void);
> > >> +extern int _tsc_is_sync;
> > >> +static inline int tsc_is_sync(void)
> > >> +{
> > >> + return _tsc_is_sync;
> > >> +}
> > >> +# else /* #ifdef CONFIG_CPU_CAVIUM_OCTEON */
> > >> +# error "64-bit get_cycles() supported only on Cavium Octeon MIPS
> > >> architectures"
> > >> +# endif /* #else #ifdef CONFIG_CPU_CAVIUM_OCTEON */
> > >> +#elif defined(CONFIG_HAVE_GET_CYCLES_32)
> > >> typedef unsigned int cycles_t;
> > >>
> > >> -#ifdef CONFIG_HAVE_GET_CYCLES_32
> > >> static inline cycles_t get_cycles(void)
> > >> {
> > >> return read_c0_count();
> > >> @@ -66,6 +93,8 @@ static inline int tsc_is_sync(void)
> > >> return _tsc_is_sync;
> > >> }
> > >> #else
> > >> +typedef unsigned int cycles_t;
> > >> +
> > >> static inline cycles_t get_cycles(void)
> > >> {
> > >> return 0;
> > >> --
> > >> Mathieu Desnoyers
> > >> Operating System Efficiency R&D Consultant
> > >> EfficiOS Inc.
> > >> http://www.efficios.com
> > >>
> > >
>
> --
> Mathieu Desnoyers
> Operating System Efficiency R&D Consultant
> EfficiOS Inc.
> http://www.efficios.com
>
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