[ltt-dev] lttv unable to execute textDump on MIPS multicore target

[David Daney]

On 02/14/2011 06:39 AM, Mathieu Desnoyers wrote:
> [ Adding David Daney to CC list, as he may have info on Octeon CPUs with
>    non-synchronized TSCs ]
>
> * Naresh Bhat (nareshgbhat at gmail.com) wrote:
>> Hi Mathieu,
>>
>> I have backported the patch and now TSC is enabled in my kernel and also I
>> am able to boot the kernel.  But one thing I have observed is between single
>> core and multiple core boot logs is that  as following
>>

I missed the patch.

However, I would note that at the time I submitted my  MIPS patches to 
Mathieu, LTTng seemed to be working well on multi-CPU Octeon systems.


[...]
>
> timex.h:
>
> static inline void write_tsc(u32 val1, u32 val2)
> {
> #ifndef CONFIG_CPU_CAVIUM_OCTEON
>          write_c0_count(val1);
> #else
> 	write_c0_cvmcount(((unsigned long) val2<<  32UL) | (unsigned long) val1);
> #endif
>          /* Arrange for an interrupt in a short while */
>          write_c0_compare(read_c0_count() + DELAY_INTERRUPT);
> }
>

This is not correct.  The main clocksource as well as sched_clock() 
which is used by ftrace and the scheduler are all driven by c0_cvmcount. 
  We take great care to properly synchronize this counter across all 
CPUs when they are brought on-line.  Anything that sets this counter can 
only make the synchronization worse, not better.

David Daney