[ltt-dev] UST cacheline_agligned

[Pierre-Marc Fournier]

On 07/05/2010 05:27 PM, Mathieu Desnoyers wrote:
> * David Goulet (david.goulet at polymtl.ca) wrote:
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>> Hi everyone,
>>
>> This is an important change for libust so some questions are raised.
>>
>> The size alignment is of course different for each architecture. So, which value
>> should be used here? (include/ust/core.h) :
>>
>> #define ____cacheline_aligned __attribute__((aligned(128)))
>>
>> Lib URCU define CACHE_LINE_SIZE to 128 and a previous discussion with Mathieu
>> Desnoyers was that typically, this value is hardcoded with the largest value
>> expected. In liburcu, the 128 size is based on Intel. Howerver, this is for
>> arch.h linked to arch_x86.h.
>>
>> So, we might actually change the default value for cache alignment base on
>> liburcu CACHE_LINE_SIZE definition since it is different for specific
>> architecture. (urcu/arch_*.h)
>
> Yep, given that ust already depends on liburcu, it would make sense to
> re-use its CACHE_LINE_SIZE definition, which is already tuned on a
> arch-specific basis.
>

Just pushed a patch that uses CACHE_LINE_SIZE from liburcu. Thanks for 
the input.

pmf