[ltt-dev] [PATCH 04/12] define sync_core for x86 PIC

[Paolo Bonzini]

Pushing/popping the reserved ebx register is surely less expensive
than a memory barrier.

Note that since ebx is a callee-save register, this is even safe for
signals (i.e. it would be safe even if we needed the value that cpuid
puts in %%ebx).

Signed-off-by: Paolo Bonzini <pbonzini at redhat.com>
---
 urcu/arch_x86.h |    8 ++++++--
 1 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/urcu/arch_x86.h b/urcu/arch_x86.h
index bc03379..eac0d19 100644
--- a/urcu/arch_x86.h
+++ b/urcu/arch_x86.h
@@ -49,9 +49,13 @@ extern "C" {
 
 /*
  * Serialize core instruction execution. Also acts as a compiler barrier.
- * Cannot use cpuid on PIC because it clobbers the ebx register;
- * error: PIC register 'ebx' clobbered in 'asm'
+ * On PIC ebx cannot be clobbered
  */
+#ifdef __PIC__
+#define sync_core()							  \
+	asm volatile("push %%ebx; cpuid; pop %%ebx"			  \
+		     : : : "memory", "eax", "ecx", "edx");
+#endif
 #ifndef __PIC__
 #define sync_core()							  \
 	asm volatile("cpuid" : : : "memory", "eax", "ebx", "ecx", "edx");
-- 
1.6.6