[ltt-dev] [PATCH 04/11] define sync_core for x86 PIC

[Mathieu Desnoyers]

* Paolo Bonzini (pbonzini at redhat.com) wrote:
> Pushing/popping the reserved ebx register is surely less expensive
> than a memory barrier.

Please add a note saying that it also works in the presence of signal
handlers, because we are not using the ebx value returned by cpuid.

It would not be correct to use this with signals enabled if we cared
about the ebx value returned by cpuid.

Thanks,

Mathieu

> 
> Signed-off-by: Paolo Bonzini <pbonzini at redhat.com>
> ---
>  urcu/arch_x86.h |    8 ++++++--
>  1 files changed, 6 insertions(+), 2 deletions(-)
> 
> diff --git a/urcu/arch_x86.h b/urcu/arch_x86.h
> index bc03379..07f2ac8 100644
> --- a/urcu/arch_x86.h
> +++ b/urcu/arch_x86.h
> @@ -49,9 +49,13 @@ extern "C" {
>  
>  /*
>   * Serialize core instruction execution. Also acts as a compiler barrier.
> - * Cannot use cpuid on PIC because it clobbers the ebx register;
> - * error: PIC register 'ebx' clobbered in 'asm'
> + * On PIC ebx cannot be clobbered
>   */
> +#ifdef __PIC__
> +#define sync_core()							  \
> +	asm volatile("push %%ebx; cpuid; pop %%ebx"			  \
> +		     : : : "memory", "eax", "ecx", "edx");
> +#endif
>  #ifndef __PIC__
>  #define sync_core()							  \
>  	asm volatile("cpuid" : : : "memory", "eax", "ebx", "ecx", "edx");
> -- 
> 1.6.6
> 
> 
> 
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-- 
Mathieu Desnoyers
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