[ltt-dev] [patch 7/9] omap trace clock

[Trilok Soni]

Hi Mathieu,

> +
> +/*
> + * Cycle counter management.
> + */
> +
> +static inline void write_pmnc(u32 val)
> +{
> +       __asm__ __volatile__ ("mcr p15, 0, %0, c9, c12, 0" : : "r" (val));
> +}
> +
> +static inline u32 read_pmnc(void)
> +{
> +       u32 val;
> +       __asm__ __volatile__ ("mrc p15, 0, %0, c9, c12, 0" : "=r" (val));
> +        return val;
> +}
> +
> +static inline void write_ctens(u32 val)
> +{
> +       __asm__ __volatile__ ("mcr p15, 0, %0, c9, c12, 1" : : "r" (val));
> +}
> +
> +static inline u32 read_ctens(void)
> +{
> +       u32 val;
> +       __asm__ __volatile__ ("mrc p15, 0, %0, c9, c12, 1" : "=r" (val));
> +       return val;
> +}
> +
> +static inline void write_intenc(u32 val)
> +{
> +       __asm__ __volatile__ ("mcr p15, 0, %0, c9, c14, 2" : : "r" (val));
> +}
> +
> +static inline u32 read_intenc(void)
> +{
> +       u32 val;
> +        __asm__ __volatile__ ("mrc p15, 0, %0, c9, c14, 2" : "=r" (val));
> +       return val;
> +}
> +
> +static inline void write_useren(u32 val)
> +{
> +       __asm__ __volatile__ ("mcr p15, 0, %0, c9, c14, 0" : : "r" (val));
> +}
> +
> +static inline u32 read_useren(void)
> +{
> +       u32 val;
> +        __asm__ __volatile__ ("mrc p15, 0, %0, c9, c14, 0" : "=r" (val));
> +       return val;
> +}
> +
> +/*
> + * Must disable counter before writing to it.
> + */
> +static inline void write_ccnt(u32 val)
> +{
> +       __asm__ __volatile__ ("mcr p15, 0, %0, c9, c13, 0" : : "r" (val));
> +}

Isn't is some of this cycle counter management code remain same for
any cortext-A8 based SoC. I mean this doesn't seem to be specific to
OMAP3 but to cortex-a8 it seems.



-- 
---Trilok Soni
http://triloksoni.wordpress.com
http://www.linkedin.com/in/triloksoni